EVAL-ADUC7060QSPZ【PDF 27/100 页】KIT DEV QUICK START ADUC7060

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ADuC7060

Table 23. I 2 C Base Address = 0xFFFF0900

Access

Default

Address

0x0900

0x0904

0x0908

0x090C

0x0910

Name

I2CMCON

I2CMSTA

I2CMRX

I2CMTX

I2CMCNT0

Byte

2

2

1

1

2

Type

R/W

R

R

W

R/W

Value

0x0000

0x0000

0x00

0x00

0x0000

Description

I 2 C master control register.

I 2 C master status register.

I 2 C master receive register.

I 2 C master transmit register.

I 2 C master read count register. Write the number of required bytes into this

register prior to reading from a slave device.

0x0914

I2CMCNT1

1

R

0x00

I 2 C master current read count register. This register contains the number of

bytes already received during a read from slave sequence.

0x0918

I2CADR0

1

R/W

0x00

Address byte register. Write the required slave address here prior to

communications.

0x091C

I2CADR1

1

R/W

0x00

Address byte register. Write the required slave address here prior to

communications. Only used in 10-bit mode.

0x0924

0x0928

0x092C

0x0930

0x0934

0x0938

0x093C

0x0940

0x0944

0x0948

0x094C

I2CDIV

I2CSCON

I2CSSTA

I2CSRX

I2CSTX

I2CALT

I2CID0

I2CID1

I2CID2

I2CID3

I2CFSTA

2

2

2

1

1

1

1

1

1

1

2

R/W

R/W

R/W

R

W

R/W

R/W

R/W

R/W

R/W

R/W

0x1F1F

0x0000

0x0000

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x0000

I 2 C clock control register. Used to configure the SCLK frequency.

I 2 C slave control register.

I 2 C slave status register.

I 2 C slave receive register.

I 2 C slave transmit register.

I 2 C hardware general call recognition register.

I 2 C Slave ID0 register. Slave bus ID register.

I 2 C Slave ID1 register. Slave bus ID register.

I 2 C Slave ID2 register. Slave bus ID register.

I 2 C Slave ID3 register. Slave bus ID register.

I 2 C FIFO status register. Used in both master and slave modes.

Table 24. SPI Base Address = 0xFFFF0A00

Address

0x0A00

0x0A04

0x0A08

0x0A0C

0x0A10

Name

SPISTA

SPIRX

SPITX

SPIDIV

SPICON

Byte

4

1

1

1

2

Access Type

R

R

W

W

R/W

Default Value

0x00000000

0x00

0xXX

0x1B

0x0000

Description

SPI status MMR.

SPI receive MMR.

SPI transmit MMR.

SPI baud rate select MMR.

SPI control MMR.

Table 25. GPIO Base Address = 0xFFFF0D00

Access

Address

0x0D00

0x0D04

0x0D08

0x0D20

0x0D24

0x0D28

0x0D2C

0x0D30

0x0D34

0x0D38

0x0D3C

0x0D40

0x0D44

0x0D48

0x0D4C

Name

GP0CON

GP1CON

GP2CON

GP0DAT

GP0SET

GP0CLR

GP0PAR

GP1DAT

GP1SET

GP1CLR

GP1PAR

GP2DAT

GP2SET

GP2CLR

GP2PAR

Byte

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

Type

RW

RW

RW

RW

W

W

R/W

RW

W

W

R/W

RW

W

W

R/W

Default Value

0x00000000

0x00000000

0x00000000

0x000000XX

0x000000XX

0x000000XX

0x00000000

0x000000XX

0x000000XX

0x000000XX

0x00000000

0x000000XX

0x000000XX

0x000000XX

0x00000000

Description

GPIO Port 0 control MMR.

GPIO Port 1 control MMR.

GPIO Port 2 control MMR.

GPIO Port 0 data control MMR.

GPIO Port 0 data set MMR.

GPIO Port 0 data clear MMR.

GPIO Port 0 pull-up disable MMR.

GPIO Port 1 data control MMR.

GPIO Port 1 data set MMR.

GPIO Port 1 data clear MMR.

GPIO Port 1 pull-up disable MMR.

GPIO Port 2 data control MMR.

GPIO Port 2 data set MMR.

GPIO Port 2 data clear MMR.

GPIO Port 2 pull-up disable MMR.

Rev. 0 | Page 27 of 100

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